This invention relates to the field of data processing, and, more particularly, to a method and apparatus for switching address generation modes in a data processing system having a central processing unit (CPU) operable with plural address generation modes.
Some CPUs or microprocessors, of a data processing system such as a personal computer, operate in plural address generation modes (addressing modes). For example, an Intel 386 (a trademark of Intel) microprocessor has two address generation modes called a real mode and a protected mode. The protected mode is divided into a paging protected mode which uses a paging function, and a non-paging mode in which the paging function is disabled. In the real mode, a value obtained from shifting a value of a CS (Code Selector) register by four bits to the left is added to an value of an IP (Instruction Pointer) register to generate a physical address. In the paging protected mode, a value of the CS is used as a pointer to a segment descriptor in a segment descriptor table. The segment descriptor table is formed in system memory. A base address contained in the segment descriptor pointed to by the CS is added to a value of the IP to generate a physical address. The paging function is performed only in the protected mode. In page conversion, an address (linear address) before the page conversion, is converted to an physical address by specifying a page table and an offset in the page table.
FIG. 3 shows an overview configuration of an Intel 386 CPU 10 which comprises six functional units. A bus interface unit 1 is an interface between the inside and outside of the CPU and accepts a fetch request from an instruction prefetch unit 2 and an execution unit 3. The instruction prefetch unit 2 fetches an instruction by using the bus interface unit 1 when the bus interface unit 1 is not involved in a bus cycle. The prefetched instruction is stored in a prefetch queue 2A of 16-byte length and waits for processing by the execution unit 3. Since the priority of bus access for prefetch is lower than that of data transfer preceded by the execution of an instruction by the execution unit 3, the execution of the instruction would not be delayed even if a prefetch function is provided. In the case where data transfer does not occur, if the prefetch queue 2A is not full of prefetched instructions, the instruction prefetch unit 2 prefetches an instruction using a bus cycle. On the other hand, if the prefetch queue 2A is full of prefetched instructions, the CPU becomes idle.
An instruction decode unit 4 removes an instruction from the prefetch queue 2A and converts it to a microcode, that is, decodes it. The decoded instruction is stored in an instruction queue 4A and waits for processing by the execution unit 3. Up to three instructions can be stored in the instruction queue 4A. The execution unit 3 executes instructions stored in the instruction queue 4A. A segmentation unit 5 converts a logical address, formed by the contents of the CS (Code Selector) and the IP (Instruction Pointer) into a 32-bit linear address of the next instruction to be executed. The CS and the IP respectively store the code segment address and offset, and are a part of a register group 3A in the execution unit 3. If the paging function is enabled, a paging unit 6 converts the linear address from the segmentation unit to a physical address. However, if the paging is not enabled, such conversion is not needed since the linear address is the same as the physical address. The paging unit 6 passes the physical address to the bus interface unit 1.
When the microprocessor is first powered up or reset, it operates in the real mode. The following steps are required to switch CPU 10 from the real mode to the paging protected mode. First, system tables in memory are initialized and registers are loaded with pointers to such tables. As shown in FIG. 4, step 11 loads or sets up the GDTR (Global Description Table Register)(not shown) of the CPU with a pointer to a GDT (Global Description Table). Step 12 loads or sets up CR3 (one of the control registers in group 3A) with a pointer to a page conversion table. Step 15 sets the CR0 control register to enable both the PE (protection enable) bit and the PG (paging enable) bit of the CR0 control register, as shown in FIG. 5. Step 15 thereby causes entry into the paging protected mode. Step 16 flushes instructions from prefetch queue 2A and sets the CS and the IP to valid values for the nest instruction to be executed. Afterwards, succeeding instructions complete conventional transitional steps to operate in the paging protected mode. A series of instructions for performing such steps are shown in FIG. 6.
With reference to FIG. 6, "LGDT MEMORY ADDRESS" is an instruction for writing or loading the pointer to the GDT from such memory address into the GDTR. "MOV EAX, MEMORY ADDRESS" and "MOV CR3,EAX" are instructions for moving the pointer to the page conversion table from the memory address thereof to the EAX register from the memory address and then transferring the pointer into the CR3 register. "MOV EAX, MEMORY ADDRESS" and "MOV CR0,EAX" are instructions for moving a value for setting the CR0 register, into the EAX register from the memory address and then transferring such value into the CR0 register. Such value enables both the PE and PG bits of the CR0 register thereby causing the address generation mode to switch and enter the paging protected mode. The CR0 and CR3 registers, etc. are a part of the register group 3A.
In the above steps for switching the address generation mode, when both the PE and PG bits of the CR0 register are enabled, transition of the address generation mode is not completed. To ensure that the address generation mode becomes completely switched, the "JMP OFFSET VALUE, SELECTOR VALUE" must be executed to flush the prefetch queue 2A and load the CS and IP with valid values of the code segment base address and offset for the next instruction to be executed. Such jump is an intersegment jump.
The normal transition from one address generation mode to another, requires two conditions to be satisfied. These conditions are (a) a linear address accords with a physical address, and (b) a page for the linear address exists (the address to be fetched resides in real memory). It is possible for an operating system (OS) program, which performs memory control, to satisfy the above conditions, but it is impossible for a program, such as a device driver program for controlling a suspend/resume mechanism which does not perform memory control, to satisfy such conditions
If the conditions (a) and (b) are not satisfied, an attempt to switch the address generation mode may cause a problem that the system will not operate normally. Such problem is caused when the CPU executes the instruction "MOV CR0,EAX" for switching the address generation mode and then tries to prefetch the next instruction "JMP OFFSET VALUE, SELECTOR VALUE" in the above example. The problem is not caused if the instruction "JMP OFFSET VALUE, SELECTOR VALUE" is already prefetched into the CPU at the time when the instruction "MOV CR0,EAX" is executed by the CPU.
A prefetch address is calculated based on current values in the CS and IP. However, if the current values of the CS and IP are the same, the prefetch address (i.e., the memory address at which an instruction to be fetched from is stored) would be different for each address generation mode since the mechanism for generating a physical address from a logical address is different for each address generation mode. Therefore, after a mode is switched by the execution of "MOV CRO,EAX", the prefetch address calculated based on the CS and IP would be different from the prefetch address based on the same CS and IP values before the transition between the modes. This causes control to be transferred to an incorrect address and system hang up to occur, or the system to malfunction or stop if a page corresponding to the calculated address does not exist.
A data processing system, such as a battery-driven notebook personal computer, usually provides a suspend/resume mechanism. However, for 386 CPUs and the like, if the suspend state occurs during the operation of system in the protected mode, the system operates in the real mode at the time of resume, after power supply to the 386 CPU and the like is turned off. Therefore, the real mode must be switched to the protected mode for each resume by a device driver program for controlling the suspend/resume mechanism. This is the reason why it is especially hoped to solve above mentioned problem.